The Itanium uses the Explicitly Parallel Instruction Computing (EPIC) architecture. EPIC is a description of the Itanium architecture, like CISC describes the Athlon and Pentium, RISC describes the PowerPC, and VLIW describes Transmeta's Crusoe. The EPIC architecture uses complex instruction wording that, in addition to the basic instruction, contains information on how to run the instruction in parallel with other instructions.

EPIC instructions are put together by the compiler into a threesome called a "bundle." Bundles instructions are sent to the CPU together. The "bundles," or their parts, are put together in an "instruction group" with other instructions. The rule for instructions to share a group, quoted from an Intel presentation, is that they do "not have read-after-write or write-after-write dependencies between them and may execute in parallel." Translation: instructions in a bundle do not affect each other with the data they are working on, so they can run together without getting in each other's way. There is no limit to the size of an instruction group, and an instruction group can begin or end in the middle of a bundle.

The instructions are actually bundled and grouped together when software is compiled. This simplifies the process of running multiple instructions at once on an Itanium CPU, allowing it to make greater use of multiple execution units without having to rely on complex on-die logic to determine what operations can run in parallel. The Itanium will still use on-die logic to improve upon instruction level parallelism, but EPIC instructions, at the minimum, provide a parallel blueprint for the Itanium processor. Of course, for this reason, compiler technology and programming algorithms will have a massive impact on Itanium performance.

In addition to grouping operations into instructions, the compiler handles several other important tasks that improve efficiency, parallelism and speed. CISC puts most of the burden of scheduling instructions onto the CPU hardware. RISC gives some of this responsibility to the compiler. VLIW removes even more load of the CPU and gives more importance to the compiler. EPIC takes things much, much further.

The compiler adds branch hints, register stack and rotation, data and control speculation, and memory hints into EPIC instructions. The compiler also uses predication. We will have more on some of these features later on, but at this point, it is enough to know that these EPIC instructions and features contribute to an increase in parallelism. These extra features are why we believe, in addition to marketing reasons, Intel coined a new term for their style of architecture, EPIC, instead of calling it VLIW (Very Long Instruction Word), which it closely resembles.